1. Field of the Invention
The present invention relates generally to integrated circuit fabrication and, more particularly, to an apparatus and method for measuring in-situ pressure across a semiconductor wafer during chemical-mechanical polishing of the wafer.
2. Description of the Related Art
In the fabrication of semiconductor devices, wafers are typically processed through a number of well known process operations. Some of the conventional process operations include oxide deposition operations, metallization sputtering operations, photolithography operations, etching operations and various types of planarization operations. Because a semiconductor device is fabricated as a multi-level device that may have a number of metallization levels (and oxide levels interdisposed), the need to planarize some of the layers before a next layer is applied becomes very apparent, particularly when the topographical variations start to increase. Consequently, if the topographical variations become too pronounced, the fabrication of additional levels may become restrictive, in that the topographical variations can limit the degree of precision needed to fabricate dimension sensitive integrated circuit devices.
One common planarization technique is referred to as chemical mechanical polishing (CMP). FIG. 1A shows a simplified drawing of a CMP apparatus 100 that is used to planarize various material layers that may be applied to a wafer 102 during a fabrication process. As is well known, CMP apparatus 100 includes a robot arm 108 that has a wafer carrier 106 for handling the wafer 102 during a polishing operation. As shown, the actual planarization of the wafer 102 occurs when the robot arm 108 lowers the wafer carrier 106 down to a polishing pad 104. To complete a planarization operation, polishing pad 104 is usually conditioned (to maintain the polishing pad's texture) before each new planarization operation is performed, and a polishing slurry having a specific pH level is applied to the surface of polishing pad 104 and is selected according to the type of material to be planarized. Once the polishing pad 104 is rotating at a given rpm, the wafer carrier 106 is lowered and placed in contact with the polishing pad 104. Once contact is made with the polishing pad 104, the CMP apparatus 100 will supply an offsetting back pressure BP to a back surface 103 of the wafer 102. A particular polishing rate will be attained depending upon the polishing pad and wafer surface material characteristics, and the offsetting back pressure.
FIG. 1B illustrates a cross-sectional view of a substrate 121 of the wafer 102 during a stage of the fabrication process prior to a CMP operation. The substrate 121 includes an oxide layer 122 upon which various structures 124 have been formed. Typically, in the fabrication of a single layer, multiple structures are formed with varying widths, geometric shapes and separations from one another. After the formation of structures 124, the fabrication process typically includes depositing an oxide layer 126 over the structures 124. As can be seen in FIG. 1B, after deposition, the surface of oxide layer 126 is not smooth but rather characterized by an irregular topography. The particular topography is driven by the underlying structures, particularly by the width, shape and separation between the structures. For example, although structure 124c and structure 124d span similar widths, FIG. 1B shows that the topography of oxide layer 126 overlying each of these devices differs. Of course, other geometric structures cause variations in the topography of oxide layer 126 that are different from those shown.
When wafer 102 is subjected to CMP to planarize the surface of oxide layer 126, the pressures experienced by that surface may vary across the surface corresponding to the particular topography. As is well known, these varying pressures will necessarily cause different polishing rates across the surface being planarized. These variations can be reduced with a CMP machine and process that is configured to programmably control the offsetting back pressure that is applied through a wafer carrier to the back side of a wafer. An example of such a CMP machine and process can be found in U.S. patent application Ser. No. 08/956,836 titled "Methods and Apparatus for Polishing Wafers" which is incorporated herein by reference.
Conventionally, the various CMP machine parameters for given structures and corresponding topography of a wafer are set by experimental testing. For example, a test wafer is typically placed within the CMP machine, and by trial and error the CMP parameters are modified until the appropriate settings are established. Unfortunately, the nature of this process may require several wafers to be successively used and likely destroyed within the CMP machine. In addition, because of the trial and error nature of the process, this process is time-consuming. For example, not only must various wafers be placed in and taken out of the CMP machine, but also the CMP machine parameters must be iteratively changed until the proper pressures and parameters are found for the correct polishing for that particular wafer topography. Further, this is done not only the first time such a topography is to be used in the CMP machine, but is also repeated after maintenance is performed on the machine, because such maintenance and re-calibration will typically alter the characteristics of the CMP processing. Additionally, the CMP machine parameters may change slowly over time through use of the machine, resulting in undesired polishing of wafers. Unfortunately, when this occurs the experimental testing may again need to be repeated to re-calibrate the process to the wafer.
In view of the foregoing, there is a need for a method and apparatus for setting CMP parameters more quickly and less expensively.